scarabaeus+ http://www.infineon.com features n two input data formats - 4:2:2 luminance and chromi- nance parallel (2 x 8 wires) - itu-r 656 data format (8 wires) n flexible compression of the input signal - digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0) - digital horizontal compression of the input signal (1.0, 2.0, 4.0) n noise reduction - motion adaptive spatial and temporal noise reduction (3d-nr) - flexible programming of the temporal noise reduction parameters - automatic measurement of the noise level (5 bit value, readable by i 2 c bus) n 3-d motion detection - high performance motion detec- tor for scan rate conversion - global motion detection flag (readable by i 2 c bus) - movie mode and phase detector (readable by i 2 c bus) n embedded memory 5 mbit embedded dram core for frame memory, (2 field memories) 192 kbit embedded dram core for line memories n flexible clock and synchro- niszation concept n scan rate conversion - motion adaptive 100/120 hz interlaced scan conversion - motion adaptive 50/60 hz progressive scan conversion - simple static interlaced and pro- gressive conversion modes for 100/120 hz interlaced or 50/60 hz progressive scan conversion: e.g. abab, aabb, aa*b*b, aaaa, bbbb, ab, aa* - large area and line flicker reduction n flexible digital vertical expansion of the output signal (1.0, ...[1/32]..., 2.0) n flexible output sync controller n signal manipulations - insertion of coloured back- ground - vertical and/or horizontal windowing with four different speed factors - flash generation (for supervis- ing applications, motion flag readable by i 2 c bus) - still field - support for split screen applica- tions (pip processor necessary) - still-in-moving picture, moving-in-still picture (pip processor necessary) - multiple picture display - tuner scan (4 and 16 times for 4:3, 12 times for 16:9 tubes) product brief scarabaeus+ sda 9400 sca n ra te converter usin g em b edded dr a m t e chnolo g y u nit s potential application the sda 9400 is a new component of the infineon megavision ? ic set for building mid and low tv sets n 100/120 hz interlaced tv sets n 50/60 hz progressive scan tv sets
how to reach us: http://www.infineon.com published by infineon technologies ag, bereich kommunikation, st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 1999 all rights reserved. attention please! the information herein is given to describe cer- tain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, in- cluding but not limited to warranties of non-in- fringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies repre- sentatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-sup- port device or system, or to affect the safety or ef- fectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. published by infineon technologies ag technical data n i 2 c bus control (400 khz) n p-mqfp-64 package n 3.3 v 5% supply voltage n 0.35 m m cmos technology n 4:2:2 processing n embedded memory - 5 mbit embedded dram core for one frame memory (2 field memories) - 192 kbit embedded dram core for line memories block dia g ram sda 9400 the sda 9400 contains all neces- sary functional blocks on a single chip: n flexible input sync controller n input format conversion n low data rate processing n memory controller n flexible output sync controller n output format conversion n high data rate processing n i 2 c bus interface n pll for frequency doubling and in a leading edge technology 5.2 mbit embedded dram for line and field memories. application example ldr vertical, horizontal decimation noise reduction and measurement motion detector motion mode and phase detection ed edram interfaces data buffer voltage control test controller ofc output format conversion hdr scan rate conversion vertical interpolation ifc input format conversion mc memory controller osc output sync controller isc input sync controller pll 1 clock doubling lm line memory lm line memory pll 2 clock doubling i 2 c i 2 c bus interface the sda 9400 is a single core ic for 100 hz containing all necessary blocks b yuvin 8 cvbs analog colour decoder + rgb input sda 9206 abacus sda 9400 scara- baeus sda 9280 display- processor e.g. sda 9488 sda 936x deflection controller cvbs hin1 vin1 y 8 uv 8 hout, vout, href y u v sync rg h-drive v-drive e/w y u v clk1=27mhz clkout pip processor application of a 100 hz tv set availability the sda 9400 and a complete documentation is available in samples 1998. mass produc- tion is scheduled for q2 1999. a dedicated engineering sup- port team is there to assist you. also an application board is available. please contact your local infineon office for further details. ordering no. b110-h7217-g1-x-7600 printed in germany ps 08993.
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